The present invention relates to semiconductor design, and more particularly, to a latency signal generating circuit for outputting a latency signal by synchronizing a read command signal, which is synchronized with an external clock signal, with an internal clock signal, and an internal clock signal generating circuit for outputting an internal clock signal by compensating an received external clock signal for an internal delay time of a semiconductor device.
In general, a semiconductor device such as a Double Data Rate Synchronous DRAM (DDR SDRAM) receives an external clock signal, generates an internal clock signal based on the received external clock signal, and uses the generated internal clock signal as a reference to synchronize various operation timings in a semiconductor device. Accordingly, the semiconductor device includes an internal clock signal generating circuit for generating an internal clock signal. Since a skew is generally generated between an external clock signal and an internal clock signal due to an internal delay of a semiconductor device, the internal clock signal generating circuit receives an external clock signal, compensates the external clock signal for the internal delay, and outputs the compensated external clock signal as an internal clock signal. A phase locked loop (PLL) or a delay locked loop (DLL) are representative internal clock signal generating circuits.
A semiconductor device receives a read command that is synchronized with an external clock signal and outputs stored data to an external device in response to an internal clock signal. That is, a semiconductor device uses an internal clock signal, not an external clock signal, to output data. Therefore, in a read operation, a semiconductor device needs to synchronize a read command, which is synchronized with an external clock signal, with an internal clock signal. That is, the synchronized clock signal is changed from an external clock signal to an internal clock signal based on the read command. Changing a synchronization target signal from a clock signal to another clock signal is referred to as domain crossing.
A semiconductor device includes various circuits for performing the domain crossing operation. Such circuits for the domain crossing include a latency generating circuit. The latency generating circuit synchronizes a read command, which was synchronized with an external clock signal, with an internal clock signal and outputs the synchronized signal as a latency signal. Herein, the latency signal, wherein the domain crossing is completed, includes CAS latency (CL) information. The semiconductor device uses the latency signal to output data to be synchronized with an external clock signal at desired point after a corresponding read command. Herein, the CAS latency includes time information from a time point of applying a corresponding read command to a time point of outputting data using one cycle of an external clock signal as a unit time. In general, the CAS latency is stored in a mode register set included in a semiconductor device.
FIG. 1 is a block diagram illustrating a delay locked loop (DLL) which is an internal clock signal generating circuit according to a prior art.
Referring to FIG. 1, the delay locked loop includes a phase comparator 110, a control signal generator 130, a variable delay unit 150, and a delay replica model 170.
The phase comparator 110 compares an external clock signal CLK_EXT with a feedback clock signal CLK_FED and outputs a detection signal DET. For example, if a phase of the feedback clock signal CLK_FED lags behind that of the external clock signal CLK_EXT, the detection signal DET becomes logic high. If a phase of the feedback clock signal CLK_FED is ahead of that of the external clock signal CLK_EXT, the detection signal DET becomes logic low.
The control signal generator 130 generates delay control signals CTR_DLY in response to the detection signal. Herein, the control signal generator 130 generates n delay control signals CTR_DLY corresponding to the number of unit delay cells included in the variable delay unit 150 where n is an integer number.
The variable delay unit 150 outputs a DLL clock signal CLK_DLL by delaying an external clock signal CLK_EXT according to the delay control signals CTR_DLY. The variable delay unit 150 includes a plurality of unit delay cells and each of the unit delay cells is enabled in response to a corresponding delay control signal CTR_DLY. Therefore, a delay amount of the external clock signal CLK_EXT is decided according to the number of enabled unit delay cells.
The delay replica model 170 generates a feedback clock signal CLK_FED by mirroring (for example, substantially identically) an internal delay of the semiconductor device to the DLL clock signal CLK_DLL outputted from the variable delay unit 150. In general, the delay replica model 170 is formed identically to a circuit of a path transferring the DLL clock signal CLK_DLL inside the semiconductor device.
The delay locked loop performs operations for making the external clock signal CLK_EXT and the feedback clock signal CLK_FED to have the same phase. Herein, making the external clock signal CLK_EXT and the feedback clock signal CLK_FED to have the same phase is referred to as locking. The locked DLL clock signal CLK_DLL is used to synchronize data. Accordingly, the data outputted after being synchronized with the DLL clock signal CLK_DLL is equivalent to data outputted after being synchronized with the external clock signal CLK_DLL.
FIG. 2 is a block diagram illustrating a latency signal generating circuit according to the prior art.
Referring to FIG. 2, the latency signal generating circuit includes a counter reset signal generator 210, an initializing unit 220, a DLL clock counter 230, an OE delay replica model 240, an external clock counter 250, a counter value latch unit 260, and a counting value comparator 270.
The counter reset signal generator 210 generates a DLL clock counter reset signal RSTb_DLL for resetting the DLL clock counter 230 by synchronizing the latency reset signal RSTb with the DLL clock signal CLK_DLL. The latency reset signal RSTb is activated by decoding external command signals such as a chip select signal /CS, a row address strobe signal /RAS, a column address strobe signal /CAS, and a write enable signal /WE. Or, the latency reset signal RSTB is activated at a time of ending a locking operation of the delay locked loop (see FIG. 1).
The initializing unit 220 provides an initial counting value INT<0:2> corresponding to CAS latency CL to the DLL clock counting unit 230. Herein, it is embodied that the initial counting unit value INT<0:2> is a 3-bit code signal. The following Table 1 shows initial counting setup values set in the initializing unit 220 corresponding to CAS latency CL3 and CAS latency CL6 and initial counting values INT<0:2> outputted from the initializing unit 220 corresponding to the initial counting setup values.
TABLE 1Initial countingCLsetup valueINT<2>INT<1>INT<0>35101441005301162010
The DLL clock counter 230 is reset in response to the DLL clock counter reset signal RSTb_DLL and counts the DLL clock signal CLK_DLL from the initial counting value INT<0:2> outputted from the initializing unit 220. That is, the DLL clock counting unit 230 generates a DLL clock counting value CNT_DLL<0:2> by counting the DLL clock signal CLK_DLL from an initial counting value set according to the CAS latency CL. For example, if the initial counting value INT<0:2> is set to 4 according to CAS latency CL, the DLL clock counter 230 outputs the DLL clock counting value CNT_DLL<0:2> counted from 4 in response to the DLL clock signal CLK_DLL.
The OE delay replica model 240 models a delay amount between the DLL clock signal CLK_DLL and the external clock signal CLK_EXT. That is, the OE delay replica model 240 generates an external clock counter reset signal RSTb_EXT by delaying the DLL clock counter reset signal RSTb_DLL. Herein, the external clock counter reset signal RSTb_EXT is synchronized with the external clock signal CLK_EXT.
The external clock counter 250 performs a counting operation in response to the external clock counter reset signal RSTb_EXT. That is, the external clock counter 250 outputs an external clock counting value CNT_EXT<0:2> counted in response to an external clock signal CLK_EXT according to the external clock counter reset signal RSTb_EXT. The initial counting value of the external clock counter 250 is set to 0 unlike the DLL clock counter 230. In other words, the external clock counter 250 outputs an external clock counting value CNT_EXT<0:2> counted from 0 in response to the external clock signal CLK_EXT after enabled according to the external clock counter reset signal RSTb_EXT.
The counting value latch unit 260 latches the external clock counting value CNT_EXT<0:2> in response to a read command signal RD_EN and outputs the latched external clock counting value LAT_CNT<0:2>. The read command signal RD_EN is a pulse signal that is activated in response to a read command. Herein, the read command is applied after being synchronized with the external clock signal CLK_EXT.
The counting value comparator 270 compares the DLL clock counting value CNT_DLL<0:2> with the latched external clock counting value LAT_CONT<0:2> and outputs a latency signal LTC activated at a time when the two values become identical. The latency signal LTC is synchronized with the DLL clock signal CLK_DLL and includes CAS latency information. In other words, the latency signal LTC is a signal generated by synchronizing a read command, which is applied after being synchronized with an external clock signal CLK_EXT, with a DLL clock signal CLK_DLL wherein CAS latency is reflected. That is, the latency signal LTC is a result of domain crossing of the read command. The latency signal LTC is used to output data with burst length information in later.
FIG. 3 is a waveform for describing an operation timing of a latency signal generating circuit of FIG. 2. For illustration purposes, CL4 indicates when CAS latency CL is 4, CL5 indicates when CAS latency CL is 5, and CL6 indicates when CAS latency CL is 6.
At first, an operation timing of a latency signal generating circuit of FIG. 2 when CAS latency CL is 4 will be described.
The initial counting value of the initializing unit 220 is set to 4 according to Table 1. Then, when a DLL clock counter reset signal RSTb_DLL is shifted to logic high, the DLL clock counting unit 230 outputs a DLL clock counting value CNT_DLL<0:2> counted from 4 which is an initial counting value in response to the DLL clock signal CLK_DLL.
Meanwhile, the OE delay replica model 240 outputs an external clock counter reset value RSTb_EXT by mirroring a delay time D to the DLL clock counter reset signal RSTb_DLL. Then, when the external clock counter reset signal RSTb_EXT is shifted to logic high, the external clock counter 250 outputs an external clock counting value CNT_EXT<0:2> counted from 0 in response to the external clock signal CLK_EXT.
If the read command signal RD_EN is activated because the read command RD is applied, the counting value latch unit 260 outputs 3 which is an external clock counting value CNT_EXT<0:2> as the latched external clock counting value LAT_CNT<0:2>. The counting value comparator 270 compares the DLL clock counting value CNT_DLL<0:2> with the latched external clock counting value LAT_CNT<0:2> and activates the latency signal LTC when the two values become identical, that is, when the DLL clock counting value CNT_DLL<0:2> becomes 3. A semiconductor device outputs data using the activated latency signal LTC when the external clock signal CLK_EXT becomes 4.
In case of CL5, the latency signal LCT is activated when the DLL clock signal CLK_DLL is 4. A semiconductor device outputs data using the activated latency signal LCT when the external clock signal CLK_EXT becomes 5. In case of CL6, the latency signal LCT is activated when the DLL clock signal CLK_DLL becomes 5. A semiconductor device outputs data using the activated latency signal LTC when the external clock signal CLK_EXT becomes 6.
Meanwhile, semiconductor devices are being manufactured for high speed operation, low power consumption, and miniaturization. However, such a semiconductor device may have the following problems.
At first, the increment of an operation frequency of a semiconductor device causes increasing CAS latency CL. Since the counting circuit having the DLL clock counter 230 and the external clock counter 250 is designed corresponding to CAS latency CL, it is necessary to design the counter circuit big if the CAS latency CL becomes large. Furthermore, it is also necessary to design a comparing circuit of the counting value comparator 270 big according to the counter. That is, a chip size of a semiconductor device disadvantageously increases.
Also, since a 4-bit counter circuit has a slower operation speed than that of a 3-bit counter circuit, the operation speed of the counter circuit become slow as the CAS latency CL increases. Then, an operation speed of the comparing circuit becomes slow as the number of bits increases. That is, a data processing speed of a semiconductor device becomes slow.
A latency signal generating circuit according to the prior art latches an external clock counting value CNT_EXT<0:2> when a read command signal RD_EN is activated. Therefore, the DLL clock counter 230 and the external clock counter 250 perform a reset operation and a counting operation before the read command signal RD_EN is activated. That is, before the read command signal RD_EN is activated, the external clock counter 250 receiving the external clock signal CLK_EXT and the DLL clock counter 230 receiving the DLL clock signal CLK_DLL continuously perform counting operations. It means a semiconductor device may waste power until the read command RD is applied. In this view, the delay locked loop DLL circuit may continuously generate the DLL clock signal CLK_DLL for the smooth operation of the latency signal generating circuit. Thus, the delay locked loop DLL circuit may waste power continuously.